Such requirements for class two capacitors often create a trap for the unwitting designer, who might naturally focus on voltage rating, size, and cost when choosing these devices. This is especially true when the top-level application is overly constrained by form factor. One can imagine the selection filtering process: start with an approximate capacitor value (i.e., 100 nF), choose a voltage rating with some reasonable headroom (i.e., 6.3 V), and finally, find the smallest surface mount (SMT) package (i.e., 0402) and cost combination to create room for other components and PCB routing.
Considering voltage rating and capacitance separately from package size may seem reasonable, but therein lies the potential trap. As capacitor sizes have grown smaller and smaller, manufacturers have developed new technologies to increase capacitance density to achieve standard value-package combinations. In doing so, dependencies have also been introduced that may create unexpected surprises during testing.